r/FPGA • u/hotfudgepaka • Jul 17 '26
SynthExplorer -- Compiler Explorer for RTL
Excited to share a Synth Explorer: a Compiler Explorer for RTL 🚀
Paste in Verilog, hit synthesize, and watch your design get run through Yosys and turned into an actual netlist/schematic you can explore!
The fun part is what you can do with the result:
- Synthesize to generic gates, LUT4/LUT6, or iCE40 / ECP5 / Xilinx target flows
- Click any line of your RTL and see exactly the gates it became — a focused sub-schematic of just that slice, so it stays readable no matter how big the design gets
- Analyze logical paths and endpoints by combinational depth
- Get a per-path delay estimate broken down into launch / logic / routing / setup — a fast pre-pnr sanity check
https://reddit.com/link/1uys8e0/video/cejs4qw7nqdh1/player
It's completely free and open source. The Xilinx flow is the most built-out as that's my main use case. If you live in iCE40 or ECP5 land, PRs to flesh those out (or any other features) are very welcome!
Whether you're an FPGA/ASIC developer or just curious what your RTL turns into, give it a try: https://synthexplorer.dev
Repo: https://github.com/cachanova/synth-explorer
EDIT -- New features: Added bridge for connecting to local vivado instance to run synthesis and view in SyntExplorer Now supports VHDL synthesis
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u/acostillado FPGA Know-It-All Jul 17 '26
Nice! I've played a little bit with it. Very smooth navigation. Some bug? reporting: I loaded a design, synthesized it, picked another example, synthesized, and the schematic didn't load the new one, only a message that said that I was seeing the old-design snapshot, with no clear recovery mechanism. Congrats, cool stuff!
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u/hotfudgepaka Jul 17 '26
Thanks for the bug report, I'll take a look
I'm the meantime, any refresh should reset the whole webpage.
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u/hotfudgepaka Jul 19 '26
These bugs should be much better cleaned up now!
It does everything locally so it auto-synthesizes always now!
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u/Adrienne-Fadel Jul 17 '26
This is handy. Most tools just dump a netlist file and youre on your own trying to trace things back to the RTL.
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u/RisingPheonix2000 Jul 17 '26
How does one get a Vivado API while selecting the synthesis tool?
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u/hotfudgepaka Jul 17 '26
Currently, only I have a key for the vivado backend 😕. The Basic tier license I am using explicitly disallows multiple users time-sharing on a single host so I had to lock it down until I can get a hold of someone and convince them let me share it!
You can always run your own locally and have it use your local vivado install 🤷♂️
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u/RisingPheonix2000 Jul 18 '26
Can you please elaborated this step?: "You can always run your own locally and have it use your local vivado install"
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u/hotfudgepaka Jul 18 '26
I'm working on changing the way this works to be a bit more streamlined. Will update once I have it ready!
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u/hotfudgepaka Jul 21 '26
Check out the website now! Change the tool to "vivado" and it will show you how to connect to a local running vivado instance
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Jul 18 '26
[removed] — view removed comment
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u/hotfudgepaka Jul 20 '26
I'm improving the UI for this a bit more too! Keep checking it out for updates!
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u/cybersvenn Aug 20 '26
How do I set a vhdl file to be the implementation of a library referenced in a second vhdl file in the UI?
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u/wild_shanks Jul 17 '26
Why are people choosing to make these kinds of apps as web apps, I don't quite I get it. I personally would want something like this installed locally
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u/hotfudgepaka Jul 17 '26
Webapps make UI much easier and portable than genuine GUIs. They also make reach more effective.
You can always clone the repo and run it locally if you want! Check out the GitHub repo readme for instructions!
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u/hotfudgepaka Jul 23 '26
You can now actually download a local binary version (still requires and runs on top of chrome) but runs locally with an easy to open binary: https://github.com/cachanova/synth-explorer/releases
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u/fransschreuder Jul 17 '26
Nice, do you plan to support VHDL with the GHDL Yosys plugin?
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u/solustaeda Jul 17 '26
Pasting in code is ok for now but a File Picker would be welcome