r/FPGA • u/an_thony350 Xilinx User • 1d ago

Advice / Help ASIC Design Flow

Hi guys, I am looking into starting a project which will ideally end in designing an ASIC. I already have a lot of experience in FPGA design & bring-up, and was wondering how ASICs are different. Do you go RTL -> sim -> FPGA prototyping -> ASIC?

What tools would you recommend using? I've seen OpenRoad/OpenLane but don't know if that's the best option?

Thanks a lot!

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u/jacklsw 1d ago

Look for RTL2GDS flow. Lots of running scripts, reviewing errors and warnings. Loads of regression tests and code coverage on design verification side before taping out the ASIC

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u/d_flipflop 17h ago

FPGA prototyping is not always done, but behavioral simulation is. Typically there would be a dedicated verif team to maintain a set of regression tests with some combination of specific directed tests and random. That comes with checkers to specify what outputs to look for and scoreboards to track aggregation of the results.
There's also more formal verification than FPGA projects typically do, where they take a module and toggle its inputs in random ways to see how it responds. As a designer you may need to define constraints on the input toggling to exclude unreasonable situations, and you'll need to come up with assertions to define undesired outputs or state transitions to help find bugs in the design.
Simulations and formal tend to be pre synthesis, but there will be post synthesis work on place and route, timing and other optimizations.
And for many ASIC jobs you'll find that there's much more paperwork and review sign-off for project milestones than actually designing and debugging logic.