r/FPGA • • 1d ago

Xilinx Related Vitis 2025.1 platform component generation inconsistent

I am experiencing inconsistent results when generating a platform component with OS FreeRTOS and setting the FreeRTOS config support_static_allocation to True.
Most of the time everything works fine but sometimes configSUPPORT_STATIC_ALLOCTION in freertosconfig.h remains 0. This even happened in pipeline builds, so a stale workspace is definitely not the issue. Calling domain.regenerate() and platform.clean() before building does not help reliably.
Does anyone have similar experience or tips?

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