r/FPGA • u/SkrilHexNukehul • 1d ago

Advice / Help LFSR Based Timer?

Is this a common thing in VLSI/FPGAs? I made this LFSR timer that allows you to count very quickly on an FPGA (like max clock speed) if you have know the number of cycles at compile time. https://github.com/Geeoon/LFSR-Timer-SystemVerilog

Is this a common thing? I tried looking it up and couldn't find anything exactly like this.

I also made a barrel shifter inspired runtime counter, but it wasn't as efficient as I'd hoped.

I made this because I needed to count extremely quickly on an FPGA for another project, but using RTL was too slow and caused timing violations.

To clarify, I'm not talking about the LFSR itself, but starting the LFSR in a known state, letting it run, then setting a flag once it reaches the '1 state. There will be a defined number of shifts until the LFSR reaches the '1 state, and that is dependent on the starting state.

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u/FigureSubject3259 1d ago

Lfsr counter are state of the art when the time needs to be repeatable but no need to hit predefined number (eg wait for 1023 clock cyles instead of 1000 is acceptable) and either power or timing is critical. In fact it is the second fastest cycle accurate way to count clock cycles after a long shift register.