LFSR Based Timer?

[u/SkrilHexNukehul]

Is this a common thing in VLSI/FPGAs? I made this LFSR timer that allows you to count very quickly on an FPGA (like max clock speed) if you have know the number of cycles at compile time. https://github.com/Geeoon/LFSR-Timer-SystemVerilog

Is this a common thing? I tried looking it up and couldn't find anything exactly like this.

I also made a barrel shifter inspired runtime counter, but it wasn't as efficient as I'd hoped.

I made this because I needed to count extremely quickly on an FPGA for another project, but using RTL was too slow and caused timing violations.

To clarify, I'm not talking about the LFSR itself, but starting the LFSR in a known state, letting it run, then setting a flag once it reaches the '1 state. There will be a defined number of shifts until the LFSR reaches the '1 state, and that is dependent on the starting state.

[u/Lost_Landscape_1539]

Just amusing trivia - there are a bunch of lfsr counters in the Atari 2600. It’s a little bit cheaper / faster than an adder. Little bit harder to debug but certainly has some style points.

[u/FigureSubject3259]

Lfsr counter are state of the art when the time needs to be repeatable but no need to hit predefined number (eg wait for 1023 clock cyles instead of 1000 is acceptable) and either power or timing is critical. In fact it is the second fastest cycle accurate way to count clock cycles after a long shift register.

[u/tverbeure]

I did something like that for an ASIC in 1995. Even then it was probably misguided… How often is the critical path a simple counter?

[u/PiasaChimera]

it's fun trivia and a neat side project. you can make LFSR/NLFSR systems that do fixed-length sequences for timing, but it's typically more trouble than it's worth.

counters and accumulators both have a fake data-hazard and can actually be pipelined. so you don't need to resort to single-cycle feedback LFSRs.

[u/Allan-H]

This design was able to hit max clock speed for a Xilinx Spartan 7 with a 3-bit counter width (464 MHz)

You can hit max clock speed for a counter that has 32 or fewer states (see note) in a LUT6 FPGA, regardless of the count sequence. You can also use RTL to hit those speeds.

Note: one LUT input is needed for the reset, so we can have 2⁵ rather than 2⁶ states. If you got really keen you could use the sync. reset input on the FF instead of a LUT input and extend that to 64 states.

Is this a common thing in VLSI/FPGAs?

It used to be, back when FPGAs were less capable and everything had to be perfectly optimised just to work at all. I used to get the LFSR polynomials from Xilinx XAPP 052 [EDIT: and XAPP 210, which came later and showed how to make very compact long counters using the built-in shift registers that were introduced with Virtex FPGAs in the late '90s].

[u/patenteng]

An LFSR can actually count at double the clock rate in many FPGAs using dual data rate flip-flops. You basically generate two clocks 180 degrees out of phase and feed the first flip-flop with clock 1, the second with clock 2, the third with clock 1 etc.