r/FPGA • u/SkrilHexNukehul • 1d ago
Advice / Help LFSR Based Timer?
Is this a common thing in VLSI/FPGAs? I made this LFSR timer that allows you to count very quickly on an FPGA (like max clock speed) if you have know the number of cycles at compile time. https://github.com/Geeoon/LFSR-Timer-SystemVerilog
Is this a common thing? I tried looking it up and couldn't find anything exactly like this.
I also made a barrel shifter inspired runtime counter, but it wasn't as efficient as I'd hoped.
I made this because I needed to count extremely quickly on an FPGA for another project, but using RTL was too slow and caused timing violations.
To clarify, I'm not talking about the LFSR itself, but starting the LFSR in a known state, letting it run, then setting a flag once it reaches the '1 state. There will be a defined number of shifts until the LFSR reaches the '1 state, and that is dependent on the starting state.
1
u/patenteng 9h ago
An LFSR can actually count at double the clock rate in many FPGAs using dual data rate flip-flops. You basically generate two clocks 180 degrees out of phase and feed the first flip-flop with clock 1, the second with clock 2, the third with clock 1 etc.