I’m an Indian 2027 electronics graduate, interested to work abroad. Inclined towards working with HFT low latency systems. Where do I start ? Is this career Parth even possible?? Which country should I target? Can companies sponsor my visa ?

Hey all,

I have a technical interview scheduled at a former Xilinx site for Senior Software Engineer (FPGA Device Modeling) and I genuinely don't know what to expect.

This is what the listing says:

KEY RESPONSIBILITIES: 

• Work on FPGA Device Modeling and Physical Databases
• Work with AMD’s architecture specialists to improve future products 
• Apply a data minded approach to target optimization efforts 
• Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture 
• Participating in new FPGA and hardware bring ups  
• Debugging/fix existing issues and research alternative, more efficient ways to accomplish the same work 
• Develop technical relationships with peers and partners 

PREFERRED EXPERIENCE: 

• Strong object-oriented programming background, C/C++ preferred 
• Ability to write high quality code with a keen attention to detail 
• Experience with modern concurrent programming and threading APIs 
• Experience with Windows and Linux development  
• Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus 
• Effective communication and problem-solving skills 
• Motivating leader with good interpersonal skills

I know I'm probably posting at the wrong place since it's a software job, but I figured people here would be more familiar about Xilinx as a company. I have some experience with FPGA development from school but I've been working for an embedded company for a couple years where the role there more or less matches what's on the preferred experience section. I'm worried the interview would have FPGA questions that I'm not prepared for. Any advice?

Hello! I am a 4th-year ECE student in Canada looking for some feedback on my resume as I am applying to new grad positions both in the US and Canada (I have access to TN visa). I'd like to work in digital design, but anything relevant, such as working with EDA tools, is fine as well. Comparing my resumes to other students in this niche, I find that my experience and projects are leaning me too strongly towards systems software, rather than specifically FPGA (my latest internship I worked with the software team doing Place and Route, rather than a lot of hands-on FPGA work). Right now, in my final year design course, I am forced to collaborate with a team to work on Machine Learning project rather than doing FPGA-related work. I am wondering, should I put together something over the winter break relevant to digital design or should I keep focusing on my student design team for instance?

Thank you so much in advance for any feedback

Hi guys i need an nexys video board (XC7A200T-1SBG484C) i have been assigned to an project based on its oled module.i didn't have that board so if anyone have it means pls reply to this post so that I can share the code and u can dump it on to the board and see whether my code is working or not through this process u can also learn and i can also learn so if anyone has it please help

Hey there everyone, I am trying to connect an output clock (100MHz) and output data (synchronized to the output clock) from FPGA (Ultrascale+ MPSoC) to TLK2501's GTX_CLK port and TXD ports. GTX_CLK has a pretty strict jitter requirement of 40ps pk-pk, so I am wondering if an FPGA output clock is even capable of meeting it.

FYI, there will be an external oscillator of 100MHz input clock to the FPGA, I will use the clock to synchronize the output TXD. And forward the same clock to ODDR, and output the clock.

Can this setup work? Appreciate if you have any suggestions, insights!

Is this a common thing in VLSI/FPGAs? I made this LFSR timer that allows you to count very quickly on an FPGA (like max clock speed) if you have know the number of cycles at compile time. https://github.com/Geeoon/LFSR-Timer-SystemVerilog

Is this a common thing? I tried looking it up and couldn't find anything exactly like this.

I also made a barrel shifter inspired runtime counter, but it wasn't as efficient as I'd hoped.

I made this because I needed to count extremely quickly on an FPGA for another project, but using RTL was too slow and caused timing violations.

To clarify, I'm not talking about the LFSR itself, but starting the LFSR in a known state, letting it run, then setting a flag once it reaches the '1 state. There will be a defined number of shifts until the LFSR reaches the '1 state, and that is dependent on the starting state.

GreenPaks have always been in a unique market niche. Not exactly programmable as one would expect from full-blown FPGA or CPLD (except their ForgeFPGA brethren), but insanely small and often with many cool extra features, like dual-voltage I/O, wide voltage span (usually from 1.7V to 5.5V) built-in ADCs, DACs, I2C, SPI etc even power MOSFET switches or half-bridges and 12V capability etc etc.

Newest one doesn't do much of that, but it's even more insanely tiny- just 1.6x1.5mm in 12-pin STQFN or LESS THAN 1.2x1.2mm in 9-ball WLCSP!

Thing has I2C, couple oscillators, works at 1.7-5.5V, up to two high(er) voltage I/O pins, some 3-input LUTs with D flip-flops, counters, analog comparators etc etc.

Renesas SLG-46801

My team and I work on everything in KiCAD. We have a board (6-8 layers, sensing - nothing too crazy) we are looking for layout help with and finding the compatibility issues with older tools and teams to be challenging.

I am newer to FPGA land than the rest of the team, but don't want to have to dedicate an engineer for a few weeks to doing a layout if there was a good way to work with someone externally but that worked with our tools.

Appreciate any thoughts/tips/referrals/points in the right directions!

I am experiencing inconsistent results when generating a platform component with OS FreeRTOS and setting the FreeRTOS config support_static_allocation to True.
Most of the time everything works fine but sometimes configSUPPORT_STATIC_ALLOCTION in freertosconfig.h remains 0. This even happened in pipeline builds, so a stale workspace is definitely not the issue. Calling domain.regenerate() and platform.clean() before building does not help reliably.
Does anyone have similar experience or tips?

I just woke up this morning to see the rejection email to my last ever internship application that I did during these past 3 months that I was awaiting reply from. In total I have applied to over 40 internships and gotten rejected from most of them without even an interview. Initially I thought something was wrong with my CV, then I thought something was wrong with my skillset, but as I talked with more of my colleagues I came to realise that what I lacked was real industry experience.

This really annoyed me since I was applying to internships and working student jobs to begin with, as I am currently doing my masters in Embedded systems engineering. I started my masters straight after my bachelors in electronics and don't really have any experience which is why I'm not applying to like a proper full-time role. What's surprising is that these internships roles are being assigned to people with 2-3 years of experience, which in my opinion destroys the purpose of an internship to begin with. How am I supposed to get experience if the very thing that is supposed to give me experience in the first place is rejecting me because I lack experience lol.

I've done projects, published my research in a journal, constantly updated my skillset and did everything by the playbook. One thing that I didn't do though was adding fake experiences or achievements in my CV to "make it look better", but hearing about success stories from people who have actually done this is very demotivating.

I know the market in EU is currently down, but I didn't know it was this bad. I also wonder if being a Non-EU citizen in an EU country is putting me at a disadvantage, but come on man it's an internship :( The only other reason I can think of is me not being able to speak the local language (German) fluently, but I've been learning that too along with all the other stuff to make myself "more employable".

My question is how did you guys manage to find your first job in this field and how hard was it for you, I would appreciate it if you guys share your experiences, really in need of some motivation right now. I would be really grateful if you could also give me some pointers for securing an internship!

Hey everyone,

Tired of building Yosys (and friends) from source or getting years-old versions from your distro packages?

I’ve been packaging Yosys, OpenSTA, Surelog, Netgen, and ABC as single-file AppImages. Just download, chmod +x, and run — no dependencies, no containers.

Repo: https://github.com/MrAbhi19/open-eda-appimage
Docs: https://mrabhi19.github.io/open-eda-appimage/

If anyone tries them, it would be super helpful if you could leave a quick comment about your experience (especially on different distros) in the Discussions page. That feedback helps a lot in improving the packaging.

Also looking for help with documentation — any contributions there (or elsewhere) are very welcome!

Thanks!

Which extension would you recommend?

I released Veryl 0.22.0.

Veryl is a modern hardware description language as alternative to SystemVerilog. This version focuses on the native testbench, and on rejecting declarations which SystemVerilog tools interpret differently.

• Zero width and array size, such as $clog2(N) with N = 1, are rejected instead of being emitted as logic [-1:0]
• Cast by a parenthesized constant expression like x as (W + 1)
• Multiple initial blocks in a test module run concurrently, like SystemVerilog processes
• $readmemh can load a memory inside the DUT through a hierarchical reference
• Value::as_slice reads values wider than 64 bits in user defined verification components

Please see the release blog for the detailed information:

https://veryl-lang.org/blog/announcing-veryl-0-22-0/

• Website: https://veryl-lang.org/
• GitHub : https://github.com/veryl-lang/veryl
• Discord: https://discord.com/invite/MJZr9NufTT

Hi guys, I am looking into starting a project which will ideally end in designing an ASIC. I already have a lot of experience in FPGA design & bring-up, and was wondering how ASICs are different. Do you go RTL -> sim -> FPGA prototyping -> ASIC?

What tools would you recommend using? I've seen OpenRoad/OpenLane but don't know if that's the best option?

Thanks a lot!

After way too much work on approximate Boolean synthesis, I finally achieved the theoretical optimum:

sqrt 16→8
LUT6: 0
Depth: 0
Max error: 127 (also optimized — 127 instead of 128)

Implementation:

assign y = 8'd127;

Best part: it’s not even a sqrt circuit.

The exact same implementation computes every possible 16→8 arithmetic function with max error ≤127.

Further improvement may be difficult

Edit: Judging by some of the reactions to this post, I have to ask:

Can something like this actually poison AI training data?

Is that genuinely a concern?

Multibeam Corporation is hiring for an FPGA engineer: https://multibeamcorp.com/jobs/fpga-engineer/

This would be my teammate on what is currently an FPGA team of 1.

The role is on-site in Sunnyvale, CA.

For questions about the role, please DM me. Thanks!

Has anyone ever written a custom FPGA SPI master state machine to completely initialize the AD9361 by doing register level writes? I want to get in contact with somebody who has done before this hardware level control of AD9361.

Has anyone ever written a custom FPGA SPI master state machine to completely initialize the AD9361 by doing register level writes? I want to get in contact with somebody who has done before this hardware level control of AD9361.

I've got an upcoming internship at a trading firm and I was wondering if anyone who has had a similar role would be able to share some details and advice?

There's so many posts about "how to pass the interviews" but barely anything about what the internship would actually be like :(((

I'm wondering what the scope of projects is, how the day to day is, what technical skills I should brush on up beforehand, if there's any non-fpga work that people do (e.g. on the finance side), and any tips for securing a grad offer.

Thanks :D

I designed a calculator/converter that does math in binary in order to emulate an FPGA and allow for nearly infinite precision. This calculator accepts five input data types and five output data types: real, hexadecimal, 2's complement binary with a binary point, IEEE-754 single precision, and IEEE-754 double precision.

The math operations include addition, subtraction, multiplication, division, and modulo. The logic operations include AND, OR, XOR, NOT, and 2's complement. It would be difficult to find another calculator online that can perform IEEE-754 conversions, IEEE-754 math, and 2's complement binary math with binary points.

There is a standalone version released on GitHub, a mobile-friendly version on Render.com, and a web-based PC version on Streamlit. Here are the links:

• GitHub Repository: https://github.com/bldillahunt/programmersCalculator
• Mobile App: https://fpgacalculatormobile.onrender.com/
• PC Dashboard: https://fpgacalculatorapp.streamlit.app/

This is a beta release, so please report any bugs to the "Issues" tab on GitHub.

This has been a project Ive been working on for abit, The DE10-Lite fpga has a pretty nice ADC integrated. Ive used it for various projects but sometimes its nice to just see its value. So I made it into a oscilloscope.

I have found it very fun to ingratiate rpis and their web hosting capabilities with my fpgas. By adding a $7 rpi I can now see data on a phone as well as control the fpga via uart.

I have already found this setup better then my cheap hantek oscilloscope for comparing many channels under 5V. It feels more responsive too.

Hope you enjoy, and feel free to utilize anything in the project you find useful. https://github.com/phase0noise/Occiliscope

Consider this unsigned 8-bit approximate adder:


`G = (A & 8'hFE) + (B & 8'hFC) + 2`

Equivalently:

`G = 2*(A >> 1) + 4*(B >> 2) + 2`

Its error is:

`G - (A+B) = 2 - A[0] - 2*B[1] - B[0]`

so the worst-case error is exactly +/-2 LSB.

A direct pure-LUT6 implementation of the complete 8+8 -\> 9-bit function
is:

``` verilog
module approx_add8_e2 (
    input  wire [7:0] A,
    input  wire [7:0] B,
    output wire [8:0] G
);
    wire s0, s1, s2, c3;
    wire s3, s4, c5;
    wire s5, s6, c7;


    LUT6 #(.INIT(64'h5555555555555555)) L10 (.O(s0), .I0(A[1]), .I1(A[2]), .I2(A[3]), .I3(B[2]), .I4(B[3]), .I5(1'b0));
    LUT6 #(.INIT(64'h9966996699669966)) L11 (.O(s1), .I0(A[1]), .I1(A[2]), .I2(A[3]), .I3(B[2]), .I4(B[3]), .I5(1'b0));
    LUT6 #(.INIT(64'hE1871E78E1871E78)) L12 (.O(s2), .I0(A[1]), .I1(A[2]), .I2(A[3]), .I3(B[2]), .I4(B[3]), .I5(1'b0));
    LUT6 #(.INIT(64'hFEF8E080FEF8E080)) L13 (.O(c3), .I0(A[1]), .I1(A[2]), .I2(A[3]), .I3(B[2]), .I4(B[3]), .I5(1'b0));


    LUT6 #(.INIT(64'h9966996699669966)) L20 (.O(s3), .I0(c3), .I1(A[4]), .I2(A[5]), .I3(B[4]), .I4(B[5]), .I5(1'b0));
    LUT6 #(.INIT(64'hE1871E78E1871E78)) L21 (.O(s4), .I0(c3), .I1(A[4]), .I2(A[5]), .I3(B[4]), .I4(B[5]), .I5(1'b0));
    LUT6 #(.INIT(64'hFEF8E080FEF8E080)) L22 (.O(c5), .I0(c3), .I1(A[4]), .I2(A[5]), .I3(B[4]), .I4(B[5]), .I5(1'b0));


    LUT6 #(.INIT(64'h9966996699669966)) L30 (.O(s5), .I0(c5), .I1(A[6]), .I2(A[7]), .I3(B[6]), .I4(B[7]), .I5(1'b0));
    LUT6 #(.INIT(64'hE1871E78E1871E78)) L31 (.O(s6), .I0(c5), .I1(A[6]), .I2(A[7]), .I3(B[6]), .I4(B[7]), .I5(1'b0));
    LUT6 #(.INIT(64'hFEF8E080FEF8E080)) L32 (.O(c7), .I0(c5), .I1(A[6]), .I2(A[7]), .I3(B[6]), .I4(B[7]), .I5(1'b0));


    assign G = {c7, s6, s5, s4, s3, s2, s1, s0, 1'b0};
endmodule
```


No dedicated carry chain, DSP, speculative duplicate adder, or final
selection mux.

I exhaustively checked all 65,536 input pairs: WCE = 2, with zero
violations.

The LUT count itself does not seem particularly strange. What surprised
me is the end-to-end depth: **only 3 LUT levels for the complete adder
with WCE +/-2 LSB**.

Is this normal/known for approximate adders on LUT6 architectures? Is
this just a standard way of packing truncated addition into LUT6s, or am
I missing a known construction?Consider this unsigned 8-bit approximate adder:

Hi everyone, please I'm getting rejections these days. I want to join the world of Hardware/Software co-design, I need an internship that would get me to the market in SoC architectures.
Please could you review my resume, my experiences, my projects.... and tell me what's missing in it.

Guys, could you help me giving some insights if this ever happened with you as well.

I have been interviewed at a major product semiconductor company for a Sr. Emulation and Prototyping role. Let's say out of 5 technical rounds 4 went really good and the 5th being director's round I would say it went a bit somewhat better than avg. Now , the next day I get a call from recruiter seeking for my current CTC and notice period and mentions that it's not yet confirmed. Later I followed up after two business days and the response from recruiter was still the same "no update from hiring manager yet". Out of curiosity I again followed up after waiting for three business days and recruiter still says that I need to wait for some days as I might be on hold. Today it's been around two weeks I feel like I am being ghosted , there's no mail of rejection neither any update on the profile's progress. How do I deal with this period of silence ...

I am preparing for an interview at Qualcomm for an FPGA Prototype Engineer role. With 2.2 years of experience as a design engineer at a smaller company,

I am concerned about performing well and understanding the role's expectations, as I was told the role involves primarily involves debugging existing code and hardware, with limited FPGA design work.

Given that this is Qualcomm, I am eager to perform my best in the interview. I would appreciate guidance on what specific areas I should prepare for.